Design For Test

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Our Purpose is To Deliver Excellence in Service and Execution

DFT Architecture and Implementation

  1. Flow and Methodology Development

IO Testing using JTAG/BSCAN Implementation

  1. Implementation of Boundary Scan at SOC Level
  2. Expertise in IEEE1149.1 and IEEE1149.6 Standards

Memory Testing using MBIST Implementation

  1. MBIST Implementation with and without repair
  2. Simulation and Debug at Timing and No-timing Simulations

Scan Implementation with and without Compression

  1. Implementation of Hierarchical and Flat Scan for Small and Multi-million Gates Design
  2. LBIST Implementation and Spyglass at RTL Level
  3. LEC for Scan Netlist
  4. IJTAG Implementation at Block and SOC Level

ATPG Pattern Generation for Different Fault Models

  1. ATPG Pattern Generation for Stuck-at, Transition, Bridging and Cell aware Fault Model and Extensive Coverage Analysis at Block Level and SOC Level
  2. Low Power Pattern Generation, Pattern Optimization and TPI Analysis
  3. Pattern Retargeting at SOC Level

DFT Validation

  1. Simulations at Timing and No-timing
  2. DFX Validation at RTL and Gate Level
  3. Analog BIST Simulations

Post Silicon Debug and ATE Support

  1. Post Silicon Support and ATE Bring up
  2. ATE Board Design and Bring up
  3. Test Program Development and Testing in different types of testers like Advantest 93K and Production support

DFT Flow