Physical Design & SignOff

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Our Purpose is To Deliver Excellence in Service and Execution


  1. Setting up the Synthesis Flow
  2. Developing Constraints
  3. Logic and Physical Aware Synthesis Using Industry Standard Tools

Physical Design (RTL - GDSII)

  1. RTL Synthesis (Logical & Physical aware)
  2. Design For test (Scan, MBIST, ATPG)
  3. Library Quality Checks, IP Validation
  4. Die Size Estimation (Bump and Ball requirement, MFU)
  5. IO Planning, Floor Planning, Partitioning
  6. Power Planning and Low Power Strategy
  7. Place & Route
  8. Clock Tree Synthesis
  9. Design for Manufacture (Metal Fill, Spare Cells, Decap Cells)
  10. Power Analysis (EM/IR)
  11. Physical Verification (DRC, LVS, ERC, ANTENNA, PERC, XOR)
  12. Low Power Checks (CLP) & Formality (LEC)
  13. Full Chip/Partition Timing Closure, MMMC Signoff
  14. ECO Iteration (Functional & Timing Fixes)

Static Timing Analysis (STA)

  1. Setting up the STA flow
  2. Develop Timing Constraints for Multiple Modes
  3. Timing Analysis for Multi Modes & Multi Corners
  4. Timing ECOs using TSO or DMSA
  5. SI Analysis

Logic Equivalence Check (LEC)

  1. Setting up the LEC flow for both Functional and CLP
  2. Block Level and Top Level LEC Runs
  3. Analysis & Debug skills for Complex Issues

Physical Design Flow